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LOSTCIRCUITS

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 nVidia NV30
Dispelling some Rumors
(Editorial by MS, August 20, 2002)

nVidia NV30, a Perspective on Rumors

As we have recently learned, nVidia has taped out the nV30 core about two weeks ago. "As we have learned" means that nVivia strictly abides by their policy to not comment on tape-out dates, yields or any other related issues so we cannot even confirm whether tape-out has really happened or not. We still have a commitment from Jen Hsun Huang to bring the NV30 to market by December this year. The reason for this short editorial is that there appears to be some confusion over what is going on, reports have claimed poor yields of the first wafers at TSMC in Taiwan. However, there also appears to be some mixup regarding current parlance in the foundry business. For example, tape-out means the shipping date of the data base used to pattern the first layer of silicon and is several weeks away from even first silicon.

For the record, tape out refers to the completion of the design blue prints that still need to be converted into reticles or photomasks to provide the pattern for the actual metal and silicon layers. Manufacturing the wafers will further take some time, the iron rule in the semiconductor business is "you can't hurry physics". So when can we expect first silicon and how representative will it be for the real NV30 core or are we at this point expecting a one-hit-wonder to be followed up in the distant future only? Read on ....


Overall, what it comes down to is, that if the tape out happened 1-2 weeks ago, nVidia will have a handful of first silicon by mid - end September, more likely end of September. All manpower will be allocated to test the die and validate that the product meets the design goal. If they are lucky, the CAD program did not make any mistakes converting the tape into wafer data, otherwise they might get one huge short and the thing will glow in the dark or else too many no-connects and the thing simply won't fire up.

One important issue to keep in mind is that the generation of a reticle or photomask used to expose the silicon is getting more complicated and prone to errors with every process shrink. That is, a 200 nm process will feature wider light slits than a 150 nm process and the difficulties increase exponentially with the inverse number of the process size. By definition, this also means that the time from tape-out to finished goods will increase by moving from a 150 nm to a 130 nm process.

After the first silicon is completed, usually some tweaks will have to be done, most likely a few of the transistor gates will need to be adjusted to improve speed or yield with the latter criteria being irrelevant for initial show-casing of a working product. Meanwhile, it is possible to go ahead and start risk production of wafers that may not be so perfect but will work after all, even with bugs. In other words, who cares whether one or the other pipeline doesn't work yet, you can always blame it on the drivers. Keep in mind that each wafer run takes about 6 weeks to add the subsequent metal and polycrystaline silicon layers.

One possibility is to use FPGA (field-programmable gate array) where certain options can be dialed-in after completing silicon but this option would only work in non-complex areas of the die since FPGA increases die size.

Everything going perfect, nVidia will have a small, rather imperfect number of NV30 in December (start the risk production in early October and get the samples 6 weeks later, that is mid November, package, assemble and tune the board for basic functionality and have them on the shelves in December. )

Depending on the outcome of the first silicon, after starting the risk wafer production, nVidia will have time to tweak the die and start multiple wafer lines in parallel, discard whatever does not work and get, whatever comes out best in terms of functionality, on the shelves, irrespective of yield. The second operational step will include yield improvement manipulations, wafers are expensive and yields will need to be in the 60-80% range to ensure profitability.

Here is the hook, though. Not only is nVidia going with a very new design, they are also going with a new process and that can cause about anything to go wrong.

This is really why any of the previous executions on time don't count here. GF3 to TI series were just minor tweaks. The same goes for the TI to GF4 series, they were all NV2x family members. But to go from the NV2 to the NV3 architecture with some radical changes AND a process shrink is a different story.

We certainly wish them luck and if they can do it, it is an incredible accomplishment.

Bottom line is that we can almost guarantee that there will be NV30 on the shelves in December but those may not be representative for the mass production that, if everything goes well, can be expected in February.

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