LOSTCIRCUITS

The X1900 Memory Architecture

On the system level, the disparity between the need for data and the actual availability has been a known issue for at least a decade. In graphics applications, the situation is somewhat similar, however, the fact that the memory configuration is fixed and all connections are soldered onto the circuit board allows for much better utilization of the memory subsystem. In addition, specific graphics memory components are much faster than their system counterparts.

This does not mean that memory bandwidth is abundant. On the contrary, even though current architectures can deliver a huge amount of data traffic, the disparity between the core and the memory subsystem still prevails, meaning that the memory bandwidth is still is a major limitation of the overall performance of the entire card.

Illustration courtesy of ATI

One way of addressing the issues is to use ultrafast on-chip memory also known as cache, however, in order to be as fast as they are, caches need to rely on transistor switching rather than on capacitor charging and a periodic refresh of data is plain and simply a no-no. This excludes the use of DRAMs, instead SRAMs are required that don't use capacitors but state changes of transistors. On the downside, the six transistors per cell make SRAM very expensive with respect to its footprint - consequently, only low densities of SRAM can be integrated on-die. Understandably, the cache will only be used for those operations where speed is absolutely vital for the graphics operations, a case in point is the Z-Buffer.

Illustration courtesy of ATI

In the case of ATI's z-buffer, the Fast Z-Clear writes 8x8 matrices on each clear. That is, instead of a single address, 64 addresses are cleared simultaneously. By extension, this speeds up the Fast Z-Clear by a factor of 64.

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