LOSTCIRCUITS

What's in a Ring Bus?

Pre-Ringbus controllers, like, for example, cross-bar switches work by receiving a request from a client and then placing the address of the data on the bus. The request is served by the memory devices by placing the data on the bus to be received by the memory controller. The controller then sends the data to the client.

In a ring bus design, things work somewhat differently. Upon getting requests from clients, the memory controller places the addresses and commands on the address and command bus but the memory devices do not send the data back to the controller. Instead, the data are broadcasted into the ring bus and each client pulls whatever they need off the bus and then send the data to one specific port on the memory controller. In order to do this, the ring bus itself needs to have enough width for all 256 data lines to be accessible by each client device. This means that a total of 256 data traces are routed around the entire core. Since these bus lines are integrated on die, there is essentially no trace length-induced delay involved. The access of the individual clients to the bus lines occurs through the use of so-called ring stops, which are also acting as interface to the memory devices.

Ring Bus Topology Overview: each Ringstop is tied to two client interfaces and two discreet memory chips. Keep in mind that the Ring Bus is only used for memory READs whereas WRITEs are executed through a standard crossbar switch.
(Illustration courtesy of ATI)

In a standard memory controller configuration, the memory controller also needs to arbitrate between reads and writes and clear the bus accordingly in between which costs bus turnaround latencies. In the case of the X1XXX memory interface, we also have a separation of read and write buses in that the ring bus is used exclusively for reads. Writes are arbitrated through a conventional crossbar switch that interfaces with the memory devices using the Ring-Stops as intermediate stage.

Example of a READ request issued by a client interface to the memory controller, which, in turn, generates the addresses and commands to retrieve the data from the appropriate memory chip. The data are then placed on the Ring Bus and the client that issued the request retrieves them.
(Illustration courtesy of ATI)

Aside from the differences in effective bandwidth that may or may not exist beyond the hypothetical model, the ring bus has one other advantage. Narrower buses are easier to manage with respect to skew and can be run at higher data rates than wide buses. Allegedly, this higher potential bus speed (ATI claims a potential doubling of the clock rate) is the greatest advantage of the new design. While we don't argue the merits of the design, the frequency doubling appears a bit exaggerated but time will tell.

Next Page:    => Sapphire X1900 XTX Tech Specs =>